LDPC-Decoder on FPGA

Electronics Club IIT Kanpur

INTRODUCTION

Let us introduce the project

Low-density parity-check (LDPC) code is a linearerror correcting code used for transmittingmessages over noisy transmission channels Byapplying a joint code and decoder designmethodology, we have developed a high-speed(3, k)-regular LDPC code partly-parallel decoderarchitecture based on which we haveimplemented a 1152-bit (3, 6)-regular LDPC codedecoder on a FPGA device.An LDPC code is defined as the null space of avery sparse M X N parity check matrix, and istypically represented by a bipartite graph ,usually called as Tanner graph. There are Nvariable (or message) nodes in one set and Mcheck (or constraint) nodes in another set in thisgraph. LDPC codes can be effectively decodedby the iterative BP or Belief-Propagation.

Architecture of the Project

Software

We have mainly used Verilog, which is ahardware description language (HDL) formodelling electronic systems. It is the mostcommonly used in the design and verification ofdigital circuits at the register-transfer level ofabstraction.For compilation and simulation,wehave used open source iverilog compiler .

BP Algorithm

It is an iterative message passing algorithm. In each round of the algorithm, messages arepassed from variable nodes to check nodes, andthen back from check nodes back to variable nodes. Since the direct implementation of BPalgorithm would have resulted in high hardware complexity due to a large number of multiplications, we have used logarithmic quantities to convert these multiplications into additions. This modification results in the Log-BP algorithm. Both BP and Log-BP algorithm realize the same decoding rule. Every decoding iteration can be performed in a fully parallel manner by mapping each check o rvariable node to one decoding processor.

Methodology

Firstly we explicitly constructed a high-girth(2,k)- regular LDPC code that exactly fitted ahigh-speed partly parallel (2,k)-regular LDPCdecoder. Then we extended this decoder to a(3,k)-regular LDPC decoder that was configuredby a set of constrained random parameters. Thisdefined a (3,k)-regular LDPC code ensemble.Each code in such an ensemble was constructedby randomly inserting certain check nodes intothe deterministic high-girth (2,k)-regular LDPCcode under the constraint specified by the decoder.

Timeline

Learning Phase

Initially we have start learning hardware programmable language such as verilog , and keep learning basic electronic module, then we moved on to LDPC code and Shannon theory, aftermath followed brief analysis of information technology and belief propagation algorithms and density evolution.

Implementation Phase

We have used a greyscale image as our input and have done image processing on it so as to add the noise. The image is then filtered by using the LDPC code so as to give the original image as the final output.

Experimentation Phase

The Experimentation Phase will be carried out when we return to the campus.

5

Mentors

9

Team Members

17

Commits

120

Crazy Ideas

15000

Lines Of Code

7200

Hours
Gallery

Check Out Some of The Photos.

PROJECT VIDEO

TEAM MEMBERS

The Project was led by 5 Mentors and 9 Team Members